Surface finishes for interconnection pads in microelectronic structures

ABSTRACT

A surface finish may be formed in a microelectronic structure, wherein the surface finish may include a multilayer interlayer structure. Thus, needed characteristics, such as compliance and electro-migration resistance, of the interlayer structure may be satisfied by different material layers, rather attempting to achieve these characteristics with a single layer. In one embodiment, the multilayer interlayer structure may comprises a two-layer structure, wherein a first layer is formed proximate a solder interconnect and comprises a material which forms a ductile joint with the solder interconnect, and a second layer comprising a material having strong electro-migration resistance formed between the first layer and an interconnection pad. In a further embodiment, third layer may be formed adjacent the interconnection pad comprising a material which forms a ductile joint with the interconnection pad.

TECHNICAL FIELD

Embodiments of the present description generally relate to the field ofmicroelectronic device fabrication, and, more particularly, to surfacefinishes formed on interconnection pads for the electrical attachment ofmicroelectronic components with solder interconnects.

BACKGROUND

Microelectronic devices are generally fabricated from variousmicroelectronic components, including, but not limited to, at least onemicroelectronic die (such as a microprocessor, a chipset, a graphicsdevice, a wireless device, a memory device, an application specificintegrated circuit, or the like), at least one passive component (suchas resistors, capacitors, inductors and the like), and at least onemicroelectronic substrate (such as interposers, motherboards, and thelike) for mounting the components. The various microelectroniccomponents may be electrically interconnected to one another throughsolder interconnects extending between interconnection pads on onemicroelectronic component to interconnection pads on anothermicroelectronic component.

The microelectronic industry is continually striving to produce everfaster and smaller microelectronic devices for use in various electronicproducts, including, but not limited to portable products, such asportable computers, digital cameras, electronic tablets, cellularphones, and the like. As the size of the microelectronic components,such as microelectronic devices and microelectronic substrates, arereduced, the current densities of the microelectronic componentsincreases, as will be understood to those skilled in the art. As thesecurrent densities increase, surface finishes, which are disposed betweeninterconnection pads and the solder interconnects, must not only form aductile interconnection or “joint” between interconnection pads and thesolder interconnects, but also have sufficiently strongelectro-migration resistance to meet maximum current (I_(max)) demandsof the smaller microelectronic components. Therefore, there is a need todevelop surface finishes and methods of fabrication thereof that canprovide a desired maximum current (I_(max)) while maintaining a ductilejoint between interconnection pads and the solder interconnects.

BRIEF DESCRIPTION OF THE DRAWINGS

The subject matter of the present disclosure is particularly pointed outand distinctly claimed in the concluding portion of the specification.The foregoing and other features of the present disclosure will becomemore fully apparent from the following description and appended claims,taken in conjunction with the accompanying drawings. It is understoodthat the accompanying drawings depict only several embodiments inaccordance with the present disclosure and are, therefore, not to beconsidered limiting of its scope. The present disclosure will bedescribed with additional specificity and detail through use of theaccompanying drawings, such that the advantages of the presentdisclosure can be more readily ascertained, in which:

FIG. 1 is a side cross sectional view of a microelectronic structure,according to an embodiment of the present description.

FIG. 2 is a side cross sectional view of an interconnection pad and asolder interconnect with a surface finish structure disposedtherebetween, as known in the art.

FIG. 3 is a side cross sectional view of an interconnection pad and asolder interconnect with a surface finish structure disposedtherebetween, according to one embodiment of the present description.

FIG. 4 is a side cross sectional view of an interconnection pad and asolder interconnect with a surface finish structure disposedtherebetween, according to another embodiment of the presentdescription.

FIG. 5 is a flow chart of a process of fabricating a microelectronicpackage, according to an embodiment of the present description.

FIG. 6 illustrates a computing device in accordance with oneimplementation of the present description.

DESCRIPTION OF EMBODIMENTS

In the following detailed description, reference is made to theaccompanying drawings that show, by way of illustration, specificembodiments in which the claimed subject matter may be practiced. Theseembodiments are described in sufficient detail to enable those skilledin the art to practice the subject matter. It is to be understood thatthe various embodiments, although different, are not necessarilymutually exclusive. For example, a particular feature, structure, orcharacteristic described herein, in connection with one embodiment, maybe implemented within other embodiments without departing from thespirit and scope of the claimed subject matter. References within thisspecification to “one embodiment” or “an embodiment” mean that aparticular feature, structure, or characteristic described in connectionwith the embodiment is included in at least one implementationencompassed within the present description. Therefore, the use of thephrase “one embodiment” or “in an embodiment” does not necessarily referto the same embodiment. In addition, it is to be understood that thelocation or arrangement of individual elements within each disclosedembodiment may be modified without departing from the spirit and scopeof the claimed subject matter. The following detailed description is,therefore, not to be taken in a limiting sense, and the scope of thesubject matter is defined only by the appended claims, appropriatelyinterpreted, along with the full range of equivalents to which theappended claims are entitled. In the drawings, like numerals refer tothe same or similar elements or functionality throughout the severalviews, and that elements depicted therein are not necessarily to scalewith one another, rather individual elements may be enlarged or reducedin order to more easily comprehend the elements in the context of thepresent description.

The terms “over”, “to”, “between” and “on” as used herein may refer to arelative position of one layer with respect to other layers. One layer“over” or “on” another layer or bonded “to” another layer may bedirectly in contact with the other layer or may have one or moreintervening layers. One layer “between” layers may be directly incontact with the layers or may have one or more intervening layers.

In the production of microelectronic structures, microelectronicpackages are generally mounted on microelectronic board/substrate thatprovides electrical communication routes between the microelectronicpackages and external components. As shown in FIG. 1, a microelectronicpackage 100 may comprise a microelectronic device 110, such as amicroprocessor, a chipset, a graphics device, a wireless device, amemory device, an application specific integrated circuit, or the like,attached to a first surface 122 of a microelectronicinterposer/substrate 120 through a plurality of solder interconnects 142in a configuration generally known as a flip-chip or controlled collapsechip connection (“C4”) configuration. The device-to-interposer/substratesolder interconnects 142 may extend from interconnection pads 114 on anactive surface 112 of the microelectronic device 110 and interconnectionpads 124 on the microelectronic interposer/substrate first surface 122.The microelectronic device interconnection pads 114 may be in electricalcommunication with integrated circuitry (not shown) within themicroelectronic device 110. The microelectronic interposer/substrate 120may include at least one conductive route 126 extending therethroughfrom at least one microelectronic interposer/substrate interconnectionpad 124 and at least one microelectronic package interconnection pad 128on or proximate a second surface 132 of the microelectronicinterposer/substrate 120. The microelectronic interposer/substrate 120may reroute a fine pitch (center-to-center distance between themicroelectronic device interconnection pads 114) of the microelectronicdevice interconnection pads 114 to a relatively wider pitch of themicroelectronic package interconnection pads 128.

The microelectronic package 100 may be attached to a microelectronicboard/substrate 150, such as printed circuit board, a motherboard, andthe like, through a plurality of solder interconnects 144, to form amicroelectronic structure 160. The package-to-board/substrate solderinterconnects 144 may extend between the microelectronic packageinterconnection pads 128 and substantially mirror-image interconnectionpads 152 on an attachment surface 154 of the microelectronicboard/substrate 150. The microelectronic board/substrate interconnectionpads 152 may be in electrical communication with conductive routes(shown as dashed lines 156) within the microelectronic board/substrate150. The microelectronic board/substrate conductive routes 156 mayprovide electrical communication routes to external components (notshown).

Both the microelectronic interposer/substrate 120 and themicroelectronic board/substrate 150 may be primarily composed of anyappropriate material, including, but not limited to, bismaleiminetriazine resin, fire retardant grade 4 material, polyimide materials,glass reinforced epoxy matrix material, and the like, as well aslaminates or multiple layers thereof. The microelectronicinterposer/substrate conductive routes 126 and the microelectronicboard/substrate conductive routes 156 may be composed of any conductivematerial, including but not limited to metals, such as copper andaluminum, and alloys thereof. As will be understood to those skilled inthe art, microelectronic interposer/substrate conductive routes 126 andthe microelectronic board/substrate conductive routes 156 may be formedas a plurality of conductive traces (not shown) formed on layers ofdielectric material (not shown), which are connected by conductive vias(not shown).

The device-to-interposer/substrate solder interconnects 142 and thepackage-to-board/substrate solder interconnects 144 can be made of anyappropriate solder material, including, but not limited to, lead/tinalloys, such as 63% tin/37% lead solder, and high tin content alloys(e.g. 90% or more tin), such as tin/bismuth, eutectic tin/silver,ternary tin/silver/copper, eutectic tin/copper, and similar alloys. Thesolder may be reflowed, either by heat, pressure, and/or sonic energy tosecure the solder between the respective interconnections pads, as willbe understood to those skilled in the art.

As shown in FIG. 2 (a close-up of any of the areas labeled A in FIG. 1),an interconnection pad 170 may represent any of the microelectronicdevice interconnection pads 114, the microelectronicinterposer/substrate interconnection pads 124, the microelectronicpackage interconnection pads 128, and the microelectronicboard/substrate interconnection pads 152 of FIG. 1, and a solderinterconnect 190 may represent any of the device-to-interposer/substratesolder interconnects 142 and the package-to-board/substrate solderinterconnects 144 of FIG. 1. As illustrated, a surface finish structure180 may be disposed between the interconnection pad 170 and the solderinterconnect 190. As known in the art, the surface finish structure 180may comprise a interlayer 182 (such as a nickel-containing metal)abutting the interconnection pad 170 (such as a copper-containingmetal), a barrier layer 184 (such as palladium-containing material) onthe interlayer 182, and an oxidation resistant and solder wetting layer186 (such as a gold-containing metal) on the barrier layer 184. As isunderstood to those skilled in the art, the interlayer 182 is utilizedto provide the characteristic of high conductivity for achieving adesired maximum current (I_(max)) and to provide the characteristic ofductility for providing sufficient flexibility to absorb any physicalshocks to the microelectronic components, such that the joint formedtherewith does not crack or break. For such a known surface finishstructure 180, consumption of the interlayer 182 is a significant causefor a decreased maximum current (I_(max)). As is known in the art,consumption of the interlayer 182 occurs when at least one component ofthe interlayer 182, such as nickel, diffuses into the solderinterconnect 190. Such consumption may be reduced by the barrier layer184, wherein the barrier layer 184 may also reduce the diffusion of atleast one component of the solder interconnect 190, such as tin, whichmay contaminate the interconnection pad 170. However, such a knownsurface finish structure 180 cannot meet future maximum current(I_(max)) requirements. Although maximum current (I_(max)) may beimproved by increasing a thickness of the barrier layer 184, such anincrease may increase brittleness thereof, which may cause the joint tobreak, and is, therefore, not a solution. Furthermore, increasing thethickness of the interlayer 182 is also not a solution, as increasingthe thickness of the interlayer 182 may cause bridging between adjacentsolder interconnects 190, as will be understood to those skilled in theart.

Embodiments of the present description include forming a multilayerinterlayer structure, rather than a single layer interlayer structure.Thus, desired characteristics, such as ductility and electro-migrationresistance, of the interlayer structure may be satisfied by differentmaterial layers, rather attempting to achieve all of the desiredcharacteristics with a single layer. In one embodiment, the multilayerinterlayer structure may comprises a two-layer structure, wherein afirst layer is formed proximate a solder interconnect and comprises amaterial which forms a ductile connection or joint with the solderinterconnect, and a second layer comprising a material having strongelectro-migration resistance formed between the first layer and aninterconnection pad. In another embodiment, the multilayer interlayerstructure may comprises a three layer structure, wherein a first layeris formed proximate a solder interconnect and comprises a material whichforms a ductile connection or joint with the solder interconnect, asecond layer comprising a material having strong electro-migrationresistance, and a third layer adjacent the interconnection padcomprising a material which forms a ductile connection or joint with theinterconnection pad, wherein the second layer is positioned between thefirst layer and the third layer. In further embodiments, multilayerinterlayer structure may comprise more than three layers to providebetter electro-migration resistance while maintaining a ductileconnection or joint with the solder interconnect or/and theinterconnection pad.

As shown in FIG. 3 (a close-up of any of the areas labeled A in FIG. 1),a surface finish 200 may include a multilayer interlayer structure 210comprising an electro-migration resistant layer 214 formed on theinterconnection pad 170 and a solder interconnect ductile layer 212formed on the electro-migration resistant layer 214. The surface finish200 may further comprise the barrier layer 184 formed on the multilayerinterlayer structure 200, and the oxidation resistant and solder wettinglayer 186 formed on the barrier layer 184.

The interconnection pad 170 may be made from any appropriate conductivematerials, such as metals. In one embodiment, the interconnection pad170 comprises copper. The solder interconnect 190 may be made of anyappropriate solder material, including, but not limited to, lead/tinalloys, such as 63% tin/37% lead solder, and high tin content alloys(e.g. 90% or more tin), such as tin/bismuth, eutectic tin/silver,ternary tin/silver/copper, eutectic tin/copper, and similar alloys.

The barrier layer 184 may be any material which resists diffusion of atleast one component of the solder interconnect ductile layer 212 intothe solder interconnect 190 and resists diffusion of at least onecomponent of the solder interconnect 190, such as tin, toward theinterconnection pad 170. In one embodiment, the barrier layer 184 maycomprise a palladium-containing material. In a specific embodiment, thebarrier layer 184 comprises palladium and phosphorus. The oxidationresistant layer 186 may be any appropriate conductive material that willreduce oxidation of the barrier layer 184 and/or the multilayerinterlayer structure 210. In one embodiment, the oxidation resistantlayer 186 comprises gold.

The solder interconnect ductile layer 212 may be any appropriatematerial, including but not limited, to a low to medium phosphoruscontent nickel material. For the purposes of the present description, alow to medium phosphorus content nickel material may be defined to be anickel material having a phosphorus content of between about 2% and 10%by weight.

The electro-migration resistant layer 214 may be any appropriatematerial that diffuses little or no material therefrom. In oneembodiment, the electro-migration resistant layer 214 may include anamorphous or nano-crystalline film, having little or no grainboundaries, exhibiting desirable electrical conductivity. For thepurpose of the present description, the amorphous or nano-crystallinefilm may include, but not limited to, a high phosphorus content nickelmaterial wherein the phosphorus content of between about 11% and 20% byweight. In another embodiment, the electro-migration resistant layer 214may include a high atomic weight metal exhibiting desired electricalconductivity. For the purposes of the present description, a high atomicweight metal may be defined to be a metal or metal alloy formed from thetransition metal group in the atomic table. In one embodiment, the highatomic weight metal may include nickel, cobalt, and/or iron. In afurther embodiment, the electro-migration resistant layer 214 mayinclude any refractory metal or its alloy with nickel, cobalt, and/oriron. In one embodiment, the refractory metal may include tungsten,molybdenum, and/or rhenium. In a further embodiment, theelectro-migration resistant layer 214 may comprise an alloy oftransitional metal, refractory metal, and/or an additional element thatmay include, but not limited to, phosphorus, exhibiting desirableelectrical conductivity. In one embodiment, the transition metal mayinclude nickel, iron, or cobalt, the refractory metal may includetungsten, molybdenum, or rhenium, and the additional element may bephosphorus.

As shown in FIG. 4 (a close-up of any of the areas labeled A in FIG. 1),the surface finish 200 may include the multilayer interlayer structure210 comprising an interconnection pad ductile layer 216 formed on theinterconnection pad 170, the electro-migration resistant layer 214formed on the interconnection pad ductile layer 216, and a solderinterconnect ductile layer 212 formed on the electro-migration resistantlayer 214. The interconnection pad ductile layer 212 may be anyappropriate material, including but not limited, to a low to mediumphosphorus content nickel material. The surface finish 200 may furthercomprise the barrier layer 184 formed on the multilayer interlayerstructure 200, and the oxidation resistant layer 186 formed on thebarrier layer 184.

FIG. 5 is a flow chart of a process 300 of fabricating a microelectronicstructure according to an embodiment of the present description. As setforth in block 302, an interconnection pad may be formed. A surfacefinish may be formed on the interconnection pad, wherein the surfacefinish comprises a multilayer interlayer structure including at leastone ductile layer and at least one electro-migration resistant layer, asset forth in block 304. As set forth in block 306, a solder interconnectformed on the surface finish.

FIG. 6 illustrates a computing device 400 in accordance with oneimplementation of the present description. The computing device 400houses a board 402. The board may include a number of microelectroniccomponents, including but not limited to a processor 404, at least onecommunication chip 406A, 406B, volatile memory 408, (e.g., DRAM),non-volatile memory 410 (e.g., ROM), flash memory 412, a graphicsprocessor or CPU 414, a digital signal processor (not shown), a cryptoprocessor (not shown), a chipset 416, an antenna, a display (touchscreendisplay), a touchscreen controller, a battery, an audio codec (notshown), a video codec (not shown), a power amplifier (AMP), a globalpositioning system (GPS) device, a compass, an accelerometer (notshown), a gyroscope (not shown), a speaker (not shown), a camera, and amass storage device (not shown) (such as hard disk drive, compact disk(CD), digital versatile disk (DVD), and so forth). Any of themicroelectronic components may be physically and electrically coupled tothe board 402. In some implementations, at least one of themicroelectronic components may be a part of the processor 404.

The communication chip enables wireless communications for the transferof data to and from the computing device. The term “wireless” and itsderivatives may be used to describe circuits, devices, systems, methods,techniques, communications channels, etc., that may communicate datathrough the use of modulated electromagnetic radiation through anon-solid medium. The term does not imply that the associated devices donot contain any wires, although in some embodiments they might not. Thecommunication chip may implement any of a number of wireless standardsor protocols, including but not limited to Wi-Fi (IEEE 802.11 family),WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE),Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT,Bluetooth, derivatives thereof, as well as any other wireless protocolsthat are designated as 3G, 4G, 5G, and beyond. The computing device mayinclude a plurality of communication chips. For instance, a firstcommunication chip may be dedicated to shorter range wirelesscommunications such as Wi-Fi and Bluetooth and a second communicationchip may be dedicated to longer range wireless communications such asGPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The term “processor” may refer to any device or portion of a device thatprocesses electronic data from registers and/or memory to transform thatelectronic data into other electronic data that may be stored inregisters and/or memory.

Any of the microelectronic components within the computing device 400may include a surface finish on a interconnection pad, wherein thesurface finish includes a multilayer interlayer structure, as describedabove.

In various implementations, the computing device may be a laptop, anetbook, a notebook, an ultrabook, a smartphone, a tablet, a personaldigital assistant (PDA), an ultra mobile PC, a mobile phone, a desktopcomputer, a server, a printer, a scanner, a monitor, a set-top box, anentertainment control unit, a digital camera, a portable music player,or a digital video recorder. In further implementations, the computingdevice may be any other electronic device that processes data.

It is understood that the subject matter of the present description isnot necessarily limited to specific applications illustrated in FIGS.1-6. The subject matter may be applied to other microelectronic deviceand assembly applications, as will be understood to those skilled in theart.

The following examples pertain to further embodiments, wherein Example 1is a microelectronic structure, comprising an interconnection pad; asurface finish on the interconnection pad, wherein the surface finishcomprises a multilayer interlayer structure including at least oneductile layer and at least one electro-migration resistant layer; and asolder interconnect on the surface finish.

In Example 2, the subject matter of Example 1 can optionally include theat least one ductile layer comprising a nickel material havingphosphorus content of between about 2% and 10% by weight.

In Example 3, the subject matter of either Example 1 or 2 can optionallyinclude the at least one electro-migration resistant layer comprising anickel material having phosphorus content of between about 11% and 20%by weight.

In Example 4, the subject matter of either Example 1 or 2 can optionallyinclude the at least one electro-migration resistant layer comprising ahigh molecular weight metal.

In Example 5, the subject matter of Example 4 can optionally include thehigh molecular weight metal being selected from the group consisting ofnickel, cobalt, and iron.

In Example 6, the subject matter of either Example 1 or 2 can optionallyinclude the electro-migration resistant layer comprising a metalselected from the group consisting of nickel, cobalt, and iron incombination with a refractory metal.

In Example 7, the subject matter of Example 6 can optionally include theelectro-migration resistant layer further comprising phosphorus, andwherein the refractory metal is selected from the group consisting oftungsten, molybdenum, and rhenium.

In Example 8, the subject matter of either Example 1 or 2 can optionallyinclude the at least one electro-migration resistant layer comprising anamorphous layer.

In Example 9, the subject matter of either Example 1 or 2 can optionallyinclude the surface finish comprising a first electro-migrationresistant layer on the interconnection pad and a ductile layer on theelectro-migration resistant layer.

In Example 10, the subject matter of Example 1 can optionally includethe surface finish comprising a first ductile layer on theinterconnection pad, an electro-migration resistant layer on the firstductile layer, and a second ductile layer on the electro-migrationresistant layer.

The following examples pertain to further embodiments, wherein Example11 is a method of fabricating a microelectronic structure, comprising:forming an interconnection pad; forming a surface finish on theinterconnection pad, wherein the surface finish comprises a multilayerinterlayer structure including at least one ductile layer and at leastone electro-migration resistant layer; and forming a solder interconnecton the surface finish.

In Example 12, the subject matter of Example 11 can optionally includeforming the surface finish comprising forming the at least one ductilelayer comprising a nickel material having phosphorus content of betweenabout 2% and 10% by weight.

In Example 13, the subject matter of either Example 11 or 12 canoptionally include forming the at least one electro-migration resistantlayer comprising forming a nickel material layer having phosphoruscontent of between about 11% and 20% by weight.

In Example 14, the subject matter of either Example 11 or 12 canoptionally include forming the surface finish comprising forming the atleast one electro-migration resistant layer comprising a high molecularweight metal.

In Example 15, the subject matter of Example 14 can optionally includethe forming the surface finish comprising forming the high molecularweight metal selected from the group consisting of nickel, cobalt, andiron.

In Example 16, the subject matter of either Example 11 or 12 canoptionally include forming the surface finish comprising forming theelectro-migration resistant selected from the group consisting ofnickel, cobalt, and iron in combination with a refractory metal.

In Example 17, the subject matter of Example 16 can optionally includeforming the electro-migration resistant layer further comprisesphosphorus, and wherein forming the refractory metal comprises metal isselected from the group consisting of tungsten, molybdenum, and rhenium.

In Example 18, the subject matter of either Example 11 or 12 canoptionally include forming the at least one electro-migration resistantlayer comprising forming an amorphous layer.

In Example 19, the subject matter of either Example 11 or 12 canoptionally include forming the surface finish comprising forming a firstelectro-migration resistant layer on the interconnection pad and forminga ductile layer on the electro-migration resistant layer.

In Example 20, the subject matter of Example 11 can optionally includethe forming the surface finish comprising forming a first ductile layeron the interconnection pad, forming an electro-migration resistant layeron the first ductile layer, and forming a second ductile layer on theelectro-migration resistant layer.

The following examples pertain to further embodiments, wherein Example21 is an electronic system, comprising a board; and a microelectronicstructure attached to the board, wherein at least one of themicroelectronic structure and the board includes an interconnection pad;a surface finish on the interconnection pad, wherein the surface finishcomprises a multilayer interlayer structure including at least oneductile layer and at least one electro-migration resistant layer; and asolder interconnect on the surface finish.

In Example 22, the subject matter of Example 21 can optionally includethe at least one ductile layer comprising a nickel material havingphosphorus content of between about 2% and 10% by weight.

In Example 23, the subject matter of either Example 21 or 22 canoptionally include the at least one electro-migration resistant layercomprising a nickel material layer having phosphorus content of betweenabout 11% and 20% by weight.

In Example 24, the subject matter of either Example 21 or 22 canoptionally include the at least one electro-migration resistant layercomprising a high molecular weight metal.

In Example 25, the subject matter of Example 24 can optionally includethe high molecular weight metal being selected from the group consistingof nickel, cobalt, and iron.

In Example 26, the subject matter of either Example 21 or 22 canoptionally include the electro-migration resistant layer comprises ametal selected from the group consisting of nickel, cobalt, and iron incombination with a refractory metal.

In Example 27, the subject matter of either Example 21 or 22 canoptionally include the electro-migration resistant layer furthercomprising phosphorus, and wherein the refractory metal is selected fromthe group consisting of tungsten, molybdenum, and rhenium.

In Example 28, the subject matter of either Example 21 or 22 canoptionally include the at least one electro-migration resistant layercomprising an amorphous layer.

In Example 29, the subject matter of either Example 21 or 22 canoptionally include the surface finish comprising a firstelectro-migration resistant layer on the interconnection pad and aductile layer on the electro-migration resistant layer.

In Example 30, the subject matter of Example 21 can optionally includethe surface finish comprising a first ductile layer on theinterconnection pad, an electro-migration resistant layer on the firstductile layer, and a second ductile layer on the electro-migrationresistant layer.

Having thus described in detail embodiments of the present description,it is understood that the present description defined by the appendedclaims is not to be limited by particular details set forth in the abovedescription, as many apparent variations thereof are possible withoutdeparting from the spirit or scope thereof.

1.-25. (canceled)
 26. A microelectronic structure, comprising: aninterconnection pad; a surface finish on the interconnection pad,wherein the surface finish comprises a multilayer interlayer structureincluding at least one ductile layer and at least one electro-migrationresistant layer; and a solder interconnect on the surface finish. 27.The microelectronic structure of claim 26, wherein the at least oneductile layer comprises a nickel material having phosphorus content ofbetween about 2% and 10% by weight.
 28. The microelectronic structure ofclaim 26, wherein the at least one electro-migration resistant layercomprises a nickel material having phosphorus content of between about11% and 20% by weight.
 29. The microelectronic structure of claim 26,wherein the at least one electro-migration resistant layer comprises ahigh atomic weight metal.
 30. The microelectronic structure of claim 29,wherein the high atomic weight metal is selected from the groupconsisting of nickel, cobalt, and iron.
 31. The microelectronicstructure of claim 26, wherein the electro-migration resistant layercomprises a metal selected from the group consisting of nickel, cobalt,and iron in combination with a refractory metal.
 32. The microelectronicstructure of claim 31, wherein the electro-migration resistant layerfurther comprises phosphorus, and wherein the refractory metal isselected from the group consisting of tungsten, molybdenum, and rhenium.33. The microelectronic structure of claim 26, wherein the at least oneelectro-migration resistant layer comprises an amorphous layer.
 34. Themicroelectronic structure of claim 26, wherein the surface finishcomprises a first electro-migration resistant layer on theinterconnection pad and a ductile layer on the electro-migrationresistant layer.
 35. The microelectronic structure of claim 26, whereinthe surface finish comprises a first ductile layer on theinterconnection pad, an electro-migration resistant layer on the firstductile layer, and a second ductile layer on the electro-migrationresistant layer.
 36. A method of fabricating a microelectronicstructure, comprising: forming an interconnection pad; forming a surfacefinish on the interconnection pad, wherein the surface finish comprisesa multilayer interlayer structure including at least one ductile layerand at least one electro-migration resistant layer; and forming a solderinterconnect on the surface finish.
 37. The method of claim 36, whereinforming the surface finish comprises forming the at least one ductilelayer comprising a nickel material having phosphorus content of betweenabout 2% and 10% by weight.
 38. The method of claim 36, wherein formingthe at least one electro-migration resistant layer comprises forming anickel material layer having phosphorus content of between about 11% and20% by weight.
 39. The method of claim 36, wherein forming the surfacefinish comprises forming the at least one electro-migration resistantlayer comprising a high atomic weight metal.
 40. The method of claim 39,wherein forming the surface finish comprises forming the high atomicweight metal selected from the group consisting of nickel, cobalt, andiron.
 41. The method of claim 36, wherein forming the surface finishcomprises forming the electro-migration resistant selected from thegroup consisting of nickel, cobalt, and iron in combination with arefractory metal.
 42. The method of claim 41, wherein forming theelectro-migration resistant layer further comprises phosphorus, andwherein forming the refractory metal comprises metal is selected fromthe group consisting of tungsten, molybdenum, and rhenium.
 43. Themethod of claim 36, wherein forming the at least one electro-migrationresistant layer comprises forming an amorphous layer.
 44. The method ofclaim 36, wherein forming the surface finish comprises forming a firstelectro-migration resistant layer on the interconnection pad and forminga ductile layer on the electro-migration resistant layer.
 45. The methodof claim 36, wherein forming the surface finish comprises forming afirst ductile layer on the interconnection pad, forming anelectro-migration resistant layer on the first ductile layer, andforming a second ductile layer on the electro-migration resistant layer.46. An electronic system, comprising: a board; and a microelectronicstructure attached to the board, wherein at least one of themicroelectronic structure and the board includes: an interconnectionpad; a surface finish on the interconnection pad, wherein the surfacefinish comprises a multilayer interlayer structure including at leastone ductile layer and at least one electro-migration resistant layer;and a solder interconnect on the surface finish.
 47. The electronicsystem of claim 46, wherein the at least one ductile layer comprises anickel material having phosphorus content of between about 2% and 10% byweight.
 48. The electronic system of claim 46, wherein the at least oneelectro-migration resistant layer comprises a nickel material havingphosphorus content of between about 11% and 20% by weight.
 49. Theelectronic system of claim 46, wherein the at least oneelectro-migration resistant layer comprises a high atomic weight metalselected from the group consisting of nickel, cobalt, and iron incombination with a refractory metal and phosphorus.
 50. The electronicsystem of claim 46, wherein the surface finish comprises a first ductilelayer on the interconnection pad, an electro-migration resistant layeron the first ductile layer, and a second ductile layer on theelectro-migration resistant layer.